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![]() ![]() ![]() The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use. The design of the CPU allows RISC computers few simple addressing modes and predictable instruction times that simplify design of the system as a whole. The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that grant access to the main memory of the computer. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. ![]() The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. ![]() In computer engineering, a reduced instruction set computer ( RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. The Sun Microsystems UltraSPARC processor is a type of RISC microprocessor. ![]()
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